FPGA Development

One of Parsec’s core competencies is the design of firmware for configurable logic devices (CPLDs and FPGAs). VHDL is used as the preferred coding-language, while graphical code-entry tools are used to speed development and enhance readability of designs. Internal IP libraries are also developed, simulated, tested and re-used across designs to accelerate time-to-market and reduce risk on new developments.

By developing in standards-based VHDL, Parsec has been able to rapidly deploy designs using Altera, Xilinx and Actel devices. Vendor and third-party IP libraries are also leveraged where suitable.

Altera’s development tools (including Quartus II, DSP Builder, Nios II and the Altera IP-suite) are frequently used to accelerate FPGA development. As a confirmation of Parsec’s proficiency, Parsec has been awarded Altera Certified Design Center status.